Hi forum!
I'm currently working on my own variant of the BE 6502. Since I got frustrated
by accidentally pulling out jumper wires, I've decided to go for a PCB design. I'd like
to ask you for a peer review and sanity check before I send this off to JLCPCB. I'll take
any sort of criticism, but I'm particularly interested in whether the address decoding,
debug device (see below) and reset circuit look like they'd work.
It's meant to use the DigiCoolThings MECB bus and board format, with a dumb backplate and peripheral boards. I
kept the ATF16v8 address decoder/glue logic because it saves space and I find it pretty
neat.
The memory map is supposed to look something like this (only the top bits are
shown)
| 15 | 14 | 13 | 12 | |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | <-RAM Start |
| 0 | 1 | 1 | 1 | <-RAM End |
| 1 | 0 | 0 | 0 | <-IO Start (b1000000000000000) |
| 1 | 0 | 0 | 1 | <-IO End (b1001111111111111) |
| 1 | 0 | 1 | 0 | <-ROM Start |
| 1 | 1 | 1 | 1 | <-ROM End |
Addressing devices in the IO range triggers the IOOE and IOCS lines (IO Output Enable and
IO Chip Select) which will select peripheral boards on the bus.
Each peripheral board will have it's own address decoding for the lower address bits.
Reset (keeping the reset line low for a sufficient amount of time) is accomplished using
a DS1233 and the datasheet reference design for that part.
Attempting to write to the ROM keeps the ROM disabled (ROM CS and OE are kept high) and
latches the data to a 74HCT273 flip-flop as a sort of primitive debug device or display.
The J2 connector is meant to attach an ArduinoMega for debugging and clocking before
getting to use the MECB DIN 41612 connector, the backplate and peripheral boards.
I've attached the schematic as an imgur link, because I'm not really that familiar with
any other image sharing platform and I don't think I can attach it directly to the forum
post.
I've also posted on r/beneater but I'd also like to hear your opinions as well
https://imgur.com/gallery/homebrew-mecb-6502-schematic-AUcB7MT